A variety of conventional flash memory devices are described in the following US patents and patent documents: U.S. Pat. Nos. 6,751,766; 7,196,946; 7,203,874; US 2006/0101193 A1; US 2007/0180346 A1.
The state of the art is believed to be described by the following publications inter alia:    [1] “Interleaving policies for flash memory”, United States Patent 20070168625    [2] “Minimization of FG-FG coupling in flash memory”, U.S. Pat. No. 6,996,004    [3] Construction of Rate (n−1)/n Punctured Convolution Code with Minimum Required SNR Criterion, Pil J. Lee, IEEE Trans. On Comm. Vol. 36, NO. 10, October 1988    [4]“Introduction to Coding Theory”, Ron M. Roth, Cambridge University Press, 2006, particularly chapters 5 and 8 re BCH.
The disclosures of all publications and patent documents mentioned in the specification, and of the publications and patent documents cited therein directly or indirectly, are hereby incorporated by reference.